1. Field of the Invention
This application relates generally to the deposition of silicon-containing materials. More particularly, this application relates to the deposition of amorphous silicon-containing films using trisilane, and to the annealing of such films to form crystalline silicon-containing films over a variety of substrates, including mixed substrates. Such deposition processes are useful in a variety of applications, e.g., semiconductor manufacturing.
2. Description of the Related Art
A variety of methods are used in the semiconductor manufacturing industry to deposit materials onto surfaces. For example, one of the most widely used methods is chemical vapor deposition (“CVD”), in which atoms or molecules contained in a vapor deposit on a surface and build up to form a film. Deposition of silicon-containing (“Si-containing”) materials using conventional silicon sources and deposition methods is believed to proceed in several distinct stages, see Peter Van Zant, “Microchip Fabrication,” 4th Ed., McGraw Hill, New York, (2000), pp. 364–365. Nucleation, the first stage, is very important and is greatly affected by the nature and quality of the substrate surface. Nucleation occurs as the first few atoms or molecules deposit onto the surface and form nuclei. During the second stage, the isolated nuclei form small islands that grow into larger islands. In the third stage, the growing islands begin coalescing into a continuous film. At this point, the film typically has a thickness of a few hundred angstroms and is known as a “transition” film. It generally has chemical and physical properties that are different from the thicker bulk film that begins to grow after the transition film is formed.
Deposition processes are usually designed to produce a particular type of bulk film morphology, e.g., single crystal, epitaxial, polycrystalline or amorphous. When using conventional silicon sources and deposition processes, nucleation is very important and critically dependent on substrate quality. For example, attempting to grow a single-crystal film on a wafer with islands of unremoved oxide will result in regions of polysilicon in the bulk film. Because of these nucleation issues, deposition of thin film Si-containing materials with similar physical properties onto substrates having two or more different types of surfaces using conventional silicon sources and deposition methods is often problematic.
For example, silicon tetrachloride (SiCl4), silane (SiH4) and dichlorosilane (SiH2Cl2) are the most widely used silicon sources in the semiconductor manufacturing industry for depositing Si-containing films, see Peter Van Zant, “Microchip Fabrication,” 4th Ed., McGraw Hill, New York, (2000), p 380–382. However, deposition using these conventional silicon sources is generally difficult to control over mixed substrates, such as surfaces containing both single crystal silicon and silicon dioxide. Control is difficult because the morphology and thickness of the resulting Si-containing film depend on both the deposition temperature and the morphology of the underlying substrate. For example, U.S. Pat. No. 4,578,142 discloses that the deposition of single crystal silicon onto a single crystal surface using SiH2Cl2 begins immediately, whereas there is a delay before non-single-crystalline deposition occurs on an adjoining silicon dioxide surface. Other deposition parameters, including total reactor pressure, reactant partial pressure and reactant flow rate can also strongly influence the quality of depositions over mixed substrates.
U.S. Pat. No. 4,578,142 discloses the use of a two stage silicon deposition/etching cycle that involves depositing single crystal silicon onto a single crystal surface and selectively etching to remove any non-single crystalline material, then repeating the cycle until the deposited single crystal silicon grows laterally across an adjoining silicon dioxide surface. Later patents refer to this deposition process as “epitaxial lateral overgrowth” (“ELO”), see U.S. Pat. Nos. 4,615,762; 4,704,186; and 4,891,092. Similar ELO techniques are disclosed in U.S. Pat. Nos. 4,557,794 and 4,755,481. Although ELO provides a method for depositing single crystal silicon over portions of an adjoining non-single crystalline surface, the ability to extend the single crystal over large areas is limited.
Solid phase epitaxy (“SPE”) is the solid phase transformation of an amorphous Si-containing material to single crystal Si-containing material, see U.S. Pat. Nos. 4,509,990; 4,808,546; 4,975,387; and 5,278,903. SPE has been used to selectively form single crystalline silicon over semiconductor substrates. For example, U.S. Pat. No. 6,346,732 discloses depositing an amorphous silicon film over a mixed substrate having a semiconductor surface and a silicon nitride surface by low pressure chemical vapor deposition (“LPCVD”) using silane as a deposition gas, then transforming the portion of the amorphous film over the semiconductor surface to single crystalline silicon by annealing. U.S. Pat. No. 6,346,732 discloses that the portion of the amorphous silicon film over the silicon nitride surface remained amorphous after annealing, see column 18, lines 47–58.
JP Patent Application No. 63166502 discloses depositing an amorphous silicon film over a mixed substrate having a single crystal silicon surface and a silicon dioxide surface by LPCVD using silane as a deposition gas, then transforming the amorphous film over both of the underlying surfaces to single crystalline silicon by annealing. This process apparently proceeds by a lateral overgrowth mechanism, in which the annealing initiates crystallization of the amorphous film in the portion of the amorphous film over the single crystal silicon surface. The portion of the amorphous silicon layer overlying the non-single crystal surface and adjoining the newly crystallized region is then transformed into single-crystal silicon by lateral overgrowth, see JP Application No. 60257703 and U.S. Pat. No. 6,274,463. Crystallization of amorphous silicon to form polycrystalline silicon can be initiated by the introduction of catalyst elements, see U.S. Pat. No. 6,162,667.
Scaling conventional CMOS transistors much below 50 nm is difficult, see S. Tang et al., “FinFET—A Quasi-Planar Double-Gate MOFSET,” IEEE International Solid-State Circuits Conference, Feb. 6, 2001 (“Tang”). Tang states that control of leakage currents requires gate dielectrics so thin and bodies doped so heavily that a process window sufficiently large for manufacturing might not be found. Double-gate MOSFET structures can overcome these and other limitations to transistor scaling. By placing a second gate on the opposite side of the device, the gate capacitance to the channel is doubled and the channel potential is better controlled by the gate electrode, thus limiting the current leakage. Various double gate structures have been proposed as well as methods for fabricating such structures. See, e.g., X. Huang et al., “Sub 50-nm FinFET: PMOS,” IEDM Technical Digest, 1999; J. M Hergenrother, “The Vertical Replaement-Gate (VRG) MOFSET: A 50-nm Vertical MOFSET with Lithography-Independent Gate Length,” IEDM Technical Digest, 1999; J. Moers et al., “Vertical Double-Gate MOSFET based on Epitaxial Growth by LPCVD,” U.S. Pat. No. 6,252,284; and U.S. Patent Application Publication Nos. 2002/0011612 and 2002/0036290.
However, the fabrication of double gate field effect transistors (“FET”) is difficult, see H.-S Wong, “Beyond the Conventional MOFSET,” IEDM Technical Digest, and/or involves complicated processing steps, see U.S. Pat. Nos. 6,372,559 and 6,365,465. It has been noted that putting a gate underneath the channel is prohibitively expensive using current techniques, see C. Edwards, “Submicron zone catalyst for end of bulk CMOS,” EETimes, May 12, 2001. In many cases, the fabrication complexity can be traced to the multiple masking, deposition, etching, and planarization steps used to create various structures over assorted underlying surfaces, particularly those having mixed morphologies.